# Auto generated by Edalize
NAME := test_quartus_0
OPTIONS := some quartus_options
DSE_OPTIONS := some dse_options

all: sta

project: $(NAME).tcl
	$(EDALIZE_LAUNCHER) quartus_sh $(OPTIONS) -t $(NAME).tcl

qsys: project
	qsys-generate qsys_file --synthesis=VERILOG --family="Cyclone V" --part=5CSXFC6D6F31C8ES --quartus-project=$(NAME)

syn: qsys
	$(EDALIZE_LAUNCHER) quartus_syn $(OPTIONS) $(NAME)

fit: syn
	$(EDALIZE_LAUNCHER) quartus_fit $(OPTIONS) $(NAME)

asm: fit
	$(EDALIZE_LAUNCHER) quartus_asm $(OPTIONS) $(NAME)

sta: asm
	$(EDALIZE_LAUNCHER) quartus_sta $(OPTIONS) $(NAME)

dse: syn
	$(EDALIZE_LAUNCHER) quartus_dse $(NAME) $(DSE_OPTIONS)

clean:
	$(EDALIZE_LAUNCHER) rm -rf *.* qdb tmp-clearbox

.PHONY: all project qsys syn fit asm sta dse clean
