# Auto generated by Edalize
NAME := test_quartus_0
OPTIONS := some quartus_options

all: sta

project: $(NAME).tcl
	quartus_sh $(OPTIONS) -t $(NAME).tcl

qsys: project
	qsys-generate qsys_file --synthesis=VERILOG --family="Cyclone V" --part=5CSXFC6D6F31C8ES --quartus-project=$(NAME)

syn: qsys
	quartus_syn $(OPTIONS) $(NAME)

fit: syn
	quartus_fit $(OPTIONS) $(NAME)

asm: fit
	quartus_asm $(OPTIONS) $(NAME)

sta: asm
	quartus_sta $(OPTIONS) $(NAME)

dse: syn
	quartus_dse $(NAME) --use-dse-file $(NAME).dse

clean:
	rm -rf *.* qdb tmp-clearbox

.PHONY: all project qsys syn fit asm sta dse clean
