Metadata-Version: 2.1
Name: pyVHDLModel
Version: 0.14.3
Summary: An abstract VHDL language model.
Home-page: https://GitHub.com/VHDL/pyVHDLModel
Author: Patrick Lehmann
Author-email: Paebbels@gmail.com
License: Apache-2.0
Project-URL: Documentation, https://VHDL.GitHub.io/pyVHDLModel
Project-URL: Source Code, https://GitHub.com/VHDL/pyVHDLModel
Project-URL: Issue Tracker, https://GitHub.com/VHDL/pyVHDLModel/issues
Keywords: Python3 VHDL Language Model Abstract
Platform: UNKNOWN
Classifier: Operating System :: OS Independent
Classifier: Intended Audience :: Developers
Classifier: Topic :: Utilities
Classifier: Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)
Classifier: Topic :: Software Development :: Code Generators
Classifier: Topic :: Software Development :: Compilers
Classifier: License :: OSI Approved :: Apache Software License
Classifier: Programming Language :: Python :: 3 :: Only
Classifier: Programming Language :: Python :: 3.6
Classifier: Programming Language :: Python :: 3.7
Classifier: Programming Language :: Python :: 3.8
Classifier: Programming Language :: Python :: 3.9
Classifier: Programming Language :: Python :: 3.10
Classifier: Development Status :: 4 - Beta
Requires-Python: >=3.6
Description-Content-Type: text/markdown
Provides-Extra: doc
Provides-Extra: all
License-File: LICENSE.md

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An abstract VHDL language model written in Python.


# Main Goals

This package provides a unified abstract language model for VHDL.
Projects reading from source files can derive own classes and implement additional logic to create a concrete language
model for their tools.

Projects consuming pre-processed VHDL data (parsed, analyzed or elaborated) can build higher level features and services
on such a model, while supporting multiple frontends.


# Use Cases

## pyVHDLModel Generators

* High-level API for [GHDL's](https://GitHub.com/ghdl/ghdl) `libghdl` offered via `pyghdl`.
* Code Document-Object-Model (Code-DOM) in [pyVHDLParser](https://GitHub.com/Paebbels/pyVHDLParser).

## pyVHDLModel Consumers

* Create graphical views of VHDL files or designs.  
	Possible candidates: [Symbolator](https://GitHub.com/kevinpt/symbolator)
* Created a (re)formatted output of VHDL.


# Examples

## List all Entities with Generics and Ports

The following tiny example is based on GHDL's [`pyGHDL.dom`](https://GitHub.com/ghdl/ghdl/tree/master/pyGHDL/dom) package implementing
pyVHDLModel.

```python
from pathlib import Path
from pyGHDL.dom.NonStandard import Design, Document

sourceFile = Path("example.vhdl")

design = Design()
library = design.GetLibrary("lib")
document = Document(sourceFile)
design.AddDocument(document, library)

for entity in document.Entities:
  print("{}".format(entity.Identifier))
  print("  generics:")
  for generic in entity.GenericItems:
    print("  - {} : {!s} {}".format(
      ", ".join([str(i) for i in generic.Identifiers]), generic.Mode, generic.Subtype)
    )
  print("  ports:")
  for port in entity.PortItems:
    print("  - {} : {!s} {}".format(
      ", ".join([str(i) for i in port.Identifiers]), port.Mode, port.Subtype)
    )
```


# Contributors

* [Patrick Lehmann](https://GitHub.com/Paebbels) (Maintainer)
* [Unai Martinez-Corral](https://GitHub.com/umarcor)
* [and more...](https://GitHub.com/VHDL/pyVHDLModel/graphs/contributors)


# License

This Python package (source code) licensed under [Apache License 2.0](LICENSE.md).  
The accompanying documentation is licensed under [Creative Commons - Attribution 4.0 (CC-BY 4.0)](doc/Doc-License.rst).

-------------------------
SPDX-License-Identifier: Apache-2.0


